1. Field of the Invention
This invention relates to integrated circuit memory devices, and, more particularly, to a design structure for a low overhead switched header power savings apparatus.
2. Description of Background
Leakage power consumption is an increasing area of concern for high performance memory arrays. Several power savings schemes have been presented in literature to address this issue. For an Application Specific Integrated Circuit (ASIC) chip, one of the paramount design considerations is area. Most power savings schemes known so far typically incur approximately a greater than ten percent (>10%) area penalty to implement the circuits. Furthermore, current schemes only address leakage savings either on the memory cells themselves or on the word line drivers.